The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to a chained array of sequential access memories which enables continuous read.
Sequential access memories have been developed which have advantages and disadvantages relative to conventional random access memories. In a sequential access memory, individual addresses are not accessible directly. The memory is organized in pages of, for example, 512 bytes each, and it is necessary to read out an entire page or half page in order to obtain the data stored at any particular address on the page. A preferred example of a sequential access memory is the Am30LV0064D UltraNAND(trademark), which is commercially available from Advanced Micro Devices, Inc. (AMD) of Sunnyvale, Calif. This memory is a Flash ROM device based on NAND architecture.
Compared to sequential access non-volatile memories, random access ROMs require more physical pins and connections, mainly for address lines, cost significantly more for the same bit density, and are not available in as high a density as sequential access memories.
Sequential access memories, on the other hand, generally require a command sequence to be written to the device in order to select and make a set of information readable. They can only read information from sequential locations in the memory until a new command sequence is written, and thus only support straight line program execution.
The AMD UltraNAND memory has a conventional read command which causes a single 512 byte page of data to be loaded into an input/output storage register in parallel, and output in series.
There is a 7 microsecond latency period at the beginning of the read operation during which the data is loaded into the register, and then data can be serially output at approximately 50 nanoseconds/byte.
The UltraNAND memory also has a xe2x80x9cgaplessxe2x80x9d read command which enables all of the memory pages to be read out with only a single 7 microsecond latency period at the beginning of the operation. This is accomplished by loading one half-page of data into one section of the register while outputting a previously loaded half-page from another section of the register in an xe2x80x9cpingpongxe2x80x9d manner until the entire memory has been read.
Although the gapless read command enables a single UltraNAND memory to be read out with only 7 microsecond latency, it does not enable a plurality of UltraNAND memories to read out continuously. For each memory that is to be read, it is necessary to individually input the read command sequence, which itself requires a substantial amount of time, and then read out the data with at least one 7 microsecond latency period for loading the first half-page of data into the input/output register.
The present invention overcomes the limitations of the prior art by providing a sequential access memory which can be chained together with similar memories to form a memory array that can be read out continuously. In accordance with the present invention, the read command sequence is loaded into all of the memories simultaneously, and the memories are then read out sequentially with only a single 7 microsecond latency at the beginning of the read operation.
More specifically, a sequential access memory structure according to the present invention includes an output bus and a plurality of sequential access memories, each of which is connected to the output bus. Each memory includes a memory array having a plurality of sequentially readable memory elements, a carry output for producing a carry signal when reading of the array has been substantially completed, and a carry input for causing reading of the array in response to a carry signal. The carry output of each memory is connected to a carry input of one other downstream memory respectively in a chain arrangement, and the carry signals cause the arrays to be read sequentially onto the output bus.
Each memory further comprises a read-write storage connected between the array and the output bus, the storage including a plurality of sections.: Data from the array is loaded into one section of the storage while data is being read from another section of the storage onto the output bus.
The sections of memory elements in the array comprise half-pages. The storage comprises two sections, each of which has a half-page of memory elements, and the carry output produces the carry signal prior to reading data from a last half-page of the array out of the storage onto the output bus. Data from the last half-page is read onto the output bus while data from a first half-page of an array of a next downstream memory is being loaded into its storage.